View LIS3LV02DL_8289030.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

january 2008 rev 2 1/48 48 LIS3LV02DL mems inertial sensor 3-axis - 2g/6g digital output low voltage linear accelerometer features 2.16 v to 3.6 v single supply operation 1.8 v compatible ios i 2 c/spi digital output interfaces programmable 12 or 16 bit data representation interrupt activated by motion programmable interrupt threshold embedded self test high shock survivability ecopack? comp liant (see section 9 ) description the LIS3LV02DL is a three axes digital output linear accelerometer that includes a sensing element and an ic interface able to take the information from the sensing element and to provide the measured acceleration signals to the external world through an i 2 c/spi serial interface. the sensing element, capable of detecting the acceleration, is manufactured using a dedicated process developed by st to produce inertial sensors and actuators in silicon. the ic interface instead is manufactured using a cmos process that allows high level of integration to design a dedicated circuit which is factory trimmed to better match the sensing element characteristics. the LIS3LV02DL has a user selectable full scale of 2g, 6g and it is capable of measuring acceleration over a bandwidth of 640 hz for all axes. the device bandwidth may be selected accordingly to the application requirements. the self-test capability a llows the user to check the functioning of the device. the device may be also configured to generate an inertial wake-up/free-fall interrupt signal when a programmable acceleration threshold is crossed at least in one of the three axes. the LIS3LV02DL is available in plastic smd package and it is specified over a temperature range extending from -40c to +85c. the LIS3LV02DL belongs to a family of products suitable for a variety of applications: ? free-fall detection ? motion activated functions in portable terminals ? antitheft systems and inertial navigation ? gaming and virtual reality input devices ? vibration monitoring and compensation lga-16 table 1. device summary order code operating temperature range [ c ] package packing LIS3LV02DL -40 to +85 lga-16 tray LIS3LV02DLtr -40 to +85 lga-16 tape and reel www.st.com
content LIS3LV02DL 2/48 content 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 lga-16 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.2 i2c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5.2 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5.3 self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 ic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.1 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.3 spi read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LIS3LV02DL content 3/48 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 offset_x (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3 offset_y (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 offset_z (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5 gain_x (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6 gain_y (1ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.7 gain_z (1bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.8 ctrl_reg1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.9 ctrl_reg2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.10 ctrl_reg3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.11 hp_filter_reset (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.12 status_reg (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.13 outx_l (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.14 outx_h (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.15 outy_l (2ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.16 outy_h (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.17 outz_l (2ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.18 outz_h (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.19 ff_wu_cfg (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.20 ff_wu_src (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.21 ff_wu_ack (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.22 ff_wu_ths_l (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.23 ff_wu_ths_h (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.24 ff_wu_duration (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.25 dd_cfg (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.26 dd_src (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.27 dd_ack (3ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.28 dd_thsi_l (3ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.29 dd_thsi_h (3dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.30 dd_thse_l (3eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.31 dd_thse_h (3fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
content LIS3LV02DL 4/48 8 typical performance characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1 mechanical characteristics at 25c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.2 mechanical characteristics derived from measurement in the -40c to +85c temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.3 electro-mechanical characteristics at 25c . . . . . . . . . . . . . . . . . . . . . . . 44 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
LIS3LV02DL list of figures 5/48 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. LIS3LV02DL electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. multiple bytes spi read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. multiple bytes spi write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. spi read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 12. x-axis zero-g level at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 13. x-axis sensitivity at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 14. y-axis zero-g level at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 15. y-axis sensitivity at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 16. z-axis zero-g level at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17. z-axis sensitivity at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 18. x-axis zero-g level change vs. temperature at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 19. x-axis sensitivity change vs. temperature at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 20. y-axis zero-g level change vs. temperature at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 21. y-axis sensitivity change vs. temperature at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 22. z-axis zero-g level change vs. temperature at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 23. z-axis sensitivity change vs. temperature at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 24. x and y axis zero-g level as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 25. z axis zero-g level as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 26. current consumption in power-down mode (vdd=3.3 v). . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 27. current consumption in operational mode (vdd=3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 28. lga-16 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
list of tables LIS3LV02DL 6/48 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 3. mechanical characteristics @ vdd=3.3 v, t=25 c unless otherwise noted . . . . . . . . . . . . 5 table 4. mechanical characteristics @ vdd=2.5 v, t=25 c unless otherwise noted . . . . . . . . . . . . 7 table 5. electrical characteristics @ vdd=3.3 v, t=25 c unless otherwise noted . . . . . . . . . . . . . 9 table 6. spi slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7. i2c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 9. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 10. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 11. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 12. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 13. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 18 table 14. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 18 table 15. registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 16. register (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 17. register description (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 18. register (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 19. register description (16h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 20. register (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 21. register description (17h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 22. register (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 23. register description (18h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 24. register (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 25. register description (19h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 26. register (1ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 27. register description (1ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 28. register (1bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 29. register description (1bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 30. register (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 31. register description (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 32. register (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 33. register description (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 34. register (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 35. register description (22h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 36. register (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 37. register description (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 38. register (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 39. register description (28h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 40. register (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 41. register description (29h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 42. register (2ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 43. register description (2ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 44. register (2bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 45. register description (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 46. register (2ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 47. register description (2ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 48. register (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LIS3LV02DL list of tables 7/48 table 49. register description (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 50. register (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 51. register description (30h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 52. register (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 53. register description (31h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 54. register (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 55. register description (34h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 56. register (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 57. register description (35h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 58. register (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 59. register description (36h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 60. register (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 61. register description (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 62. register (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 63. register description (39h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 64. register (3ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 65. register description (3ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 66. register (3dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 67. register description (3dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 68. register (3eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 69. register description (3eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 70. register (3fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 71. register description (3fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 72. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
block diagram and pin description LIS3LV02DL 8/48 1 block diagram and pin description 1.1 block diagram figure 1. block diagram 1.2 lga-16 pin description figure 2. pin connection ? charge amplifier mux y+ z+ y- z- regs a x+ x- de mux reconstruction filter ? ? array i 2 c spi cs scl/spc sda/sdo/sdi sdo control logic & interrupt gen. rdy/int reconstruction filter reconstruction filter clock trimming circuits reference self test table 2. pin description pin# name function 1 rdy/int data ready/inertial wake-up interrupt 2 sdo spi serial data output y 1 x z direction of the detectable accelerations LIS3LV02DL (top view) 1 6 7 8 9 14 15 16 cs scl/spc vdd_io sdo rdy/int gnd res vdd res vdd gnd nc ck gnd res sda/sdi/sdo
LIS3LV02DL block diagram and pin description 9/48 3 sda/ sdi/ sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 4 vdd_io power supply for i/o pads 5scl/spc i 2 c serial clock (scl) spi serial port clock (spc) 6cs spi enable i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) 7 nc internally not connected 8ck optional external clock, if not used either leave unconnected or connect to gnd 9 gnd 0 v supply 10 reserved either leave uncon nected or connect to vdd_io 11 vdd power supply 12 reserved connect to vdd 13 vdd power supply 14 gnd 0 v supply 15 reserved either leave unconnected or connect to gnd 16 gnd 0 v supply table 2. pin description pin# name function
mechanical and electrical specifications LIS3LV02DL 10/48 2 mechanical and electrical specifications 2.1 mechanical characteristics table 3. mechanical characteristics @ vdd=3.3 v, t=25 c unless otherwise noted (1) symbol parameter tes t conditions min. typ. (2) max. unit fs measurement range (3) fs bit set to 0 1.7 2.0 g fs bit set to 1 5.3 6.0 dres device resolution full-scale = 2 g odr1=40 hz 1.0 mg full-scale = 2 g odr2=160 hz 2.0 full-scale = 2 g odr3=640 hz 3.9 full-scale = 2 g odr4=2560 hz 15.6 so sensitivity full-scale = 2 g 12 bit representation 920 1024 1126 lsb/g full-scale = 6 g 12 bit representation 306 340 374 tcso sensitivity change vs temperature full-scale = 2 g 12 bit representation 0.025 %/ c off zero-g level offset accuracy (4),(5) full-scale = 2 g x, y axis -70 70 mg full-scale = 2 g z axis -90 90 full-scale = 6 g x, y axis -90 90 full-scale = 6 g z axis -100 100 lto f f zero-g level offset long term accuracy (6) full-scale = 2 g x, y axis -4.5 4.5 %fs full-scale = 2 g z axis -6 6 full-scale = 6 g x, y axis -1.8 1.8 full-scale = 6 g z axis -2.2 2.2 tcoff zero-g level change vs temperature max delta from 25c 0.2 mg/ c
LIS3LV02DL mechanical and electrical specifications 11/48 nl non linearity best fit straight line x, y axis full-scale = 2 g odr=40 hz 2 %fs best fit straight line z axis full-scale = 2 g odr=40 hz 3 crax cross axis -3.5 3.5 % v st self test output change (7),(8) full-scale= 2g x axis 250 550 900 lsb full-scale= 2 g y axis 250 550 900 lsb full-scale= 2 g z axis -100 -350 -600 lsb full-scale= 6 g x axis 80 180 300 lsb full-scale= 6 g y axis 80 180 300 lsb full-scale= 6 g z axis -30 -120 -200 lsb bw system bandwidth (9) odrx/4 hz to p operating temperature range -40 +85 c wh product weight 72 mgram 1. the product is factory calibrated at 3.3 v. t he device can be used from 2.16 v to 3.6 v 2. typical specificat ions are not guaranteed 3. verified by wafer level test and specif ication of initial offset and sensitivity 4. zero-g level offset value after msl3 preconditioning 5. offset can be eliminated by enabling the built-in high pass filter (hpf) 6. results of accelerated reliability tests 7. self test output changes with the power supply. ?self test output change? is defined as output[lsb] (self-test bit on ctrl_reg1=1) - output[lsb] (self-test bit on ctrl_reg1=0) . 1lsb=1g/1024 at 12bit representation, 2g full-scale 8. output data reach 99% of final value after 5/od r when enabling self-test mode due to device filtering 9. odrx is output data rate. refer to table 5 for specifications table 3. mechanical characteristics @ vdd=3.3 v, t=25 c unless otherwise noted (1) (continued) symbol parameter tes t conditions min. typ. (2) max. unit
mechanical and electrical specifications LIS3LV02DL 12/48 table 4. mechanical characteristics @ vdd=2.5 v, t=25 c unless otherwise noted (1) symbol parameter tes t conditions min. typ. (2) max. unit fs measurement range (3) fs bit set to 0 1.7 2.0 g fs bit set to 1 5.3 6.0 dres device resolution full-scale = 2g odr1=40hz 1.0 mg full-scale = 2g odr2=160hz 2.0 full-scale = 2g odr3=640hz 3.9 full-scale = 2g odr4=2560hz 15.6 so sensitivity full-scale = 2g 12 bit representation 920 1024 1126 lsb/g full-scale = 6g 12 bit representation 306 340 374 tcso sensitivity change vs temperature full-scale = 2g 12 bit representation 0.025 %/ c off zero-g level offset accuracy (4),(5) full-scale = 2g x, y axis -90 90 mg full-scale = 2g z axis -110 110 full-scale = 6g x, y axis -110 110 full-scale = 6g z axis -120 120 lto f f zero-g level offset long term accuracy (6) full-scale = 2g x, y axis -5.5 5.5 %fs full-scale = 2g z axis -7 7 full-scale = 6g x, y axis -2.8 2.8 full-scale = 6g z axis -3.2 3.2 tcoff zero-g level change vs temperature max delta from 25c 0.2 mg/ c
LIS3LV02DL mechanical and electrical specifications 13/48 nl non linearity best fit straight line x, y axis full-scale = 2g odr=40hz 2 %fs best fit straight line z axis full-scale = 2g odr=40hz 3 crax cross axis -3.5 3.5 % v st self test output change (7),(8) full-scale= 2g x axis 100 240 400 lsb full-scale= 2g y axis 100 240 400 lsb full-scale= 2g z axis -30 -150 -350 lsb full-scale= 6g x axis 30 80 130 lsb full-scale= 6g y axis 30 80 130 lsb full-scale= 6g z axis -10 -50 -120 lsb bw system bandwidth (9) odrx/4 hz top operating temperature range -40 +85 c wh product weight 72 mgram 1. the product is factory calibrated at 3.3 v. t he device can be used from 2.16 v to 3.6 v 2. typical specificat ions are not guaranteed 3. verified by wafer level test and specif ication of initial offset and sensitivity 4. zero-g level offset value after msl3 preconditioning 5. offset can be eliminated by enabling the built-in high pass filter (hpf) 6. results of accelerated reliability tests 7. self test output changes with the power supply. ?self test output change? is defined as output[lsb] (self-test bit on ctrl_reg1=1) - output[lsb] (self-test bit on ctrl_reg1=0) . 1lsb=1g/1024 at 12bit representation, 2g full-scale 8. output data reach 99% of final value after 5/od r when enabling self-test mode due to device filtering 9. odrx is output data rate. refer to table 5 for specifications table 4. mechanical characteristics @ vdd=2.5 v, t=25 c unless otherwise noted (1) (continued) symbol parameter tes t conditions min. typ. (2) max. unit
mechanical and electrical specifications LIS3LV02DL 14/48 2.2 electrical characteristics table 5. electrical characteristics @ vdd=3.3 v, t=25 c unless otherwise noted (1) symbol parameter tes t conditions min. typ. (2) max. unit vdd supply voltage 2.16 3.3 3.6 v vdd_io i/o pads supply voltage 1.71 vdd v idd supply current vdd = 3.3 v 0.65 0.80 ma vdd = 2.5 v 0.60 0.75 iddpdn current consumption in power-down mode 110 a vih digital high level input voltage 0.8*vdd _io v vil digital low level input voltage 0.2*vdd _io voh high level output voltage 0.9*vdd _io v vol low level output voltage 0.1*vdd _io odr1 output data rate 1 dec factor = 512 40 hz odr2 output data rate 2 dec factor = 128 160 odr3 output data rate 3 dec factor = 32 640 odr4 output data rate 4 dec factor = 8 2560 bw system bandwidth (3) odrx/4 hz to n turn-on time (4) 5/odrx s top operating temperature range -40 +85 c 1. the product is factory calibrated at 3.3 v. t he device can be used from 2.16 v to 3.6 v 2. typical specificat ions are not guaranteed 3. digital filter cut-off frequency 4. time to obtain valid data after exiting power-down mode
LIS3LV02DL mechanical and electrical specifications 15/48 2.3 communication interface characteristics 2.3.1 spi - serial peripheral interface subject to general operating conditions for vdd and top. figure 3. spi slave timing diagram (2) 2. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both input and output port 3. when no communication is on-going, data on cs, spc, sdi and sdo are driven by internal pull-up resistors table 6. spi slave timing values symbol parameter value (1) 1. values are guaranteed at 8 mhz clock frequency for spi with both 4 and 3 wires, based on characterization results, not tested in production unit min max tc(spc) spi clock cycle 125 ns fc(spc) spi clock frequency 8 mhz tsu(cs) cs setup time 5 ns th(cs) cs hold time 10 tsu(si) sdi input setup time 5 th(si) sdi input hold time 15 tv(so) sdo valid output time 55 th(so) sdo output hold time 7 tdis(so) sdo output disable time 50 spc cs sdi sdo t su(cs) t v(so) t h(so) t h(si) t su(si) t h(cs) t dis(so) t c(spc) msb in msb out lsb out lsb in (3) (3) (3) (3) (3) (3) (3) (3)
mechanical and electrical specifications LIS3LV02DL 16/48 2.3.2 i 2 c - inter ic control interface subject to general operating conditions for vdd and top. figure 4. i 2 c slave timing diagram (4) 4.measurement points are done at 0.2vdd_io and 0.8vdd_io, for both port table 7. i2c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min max min max f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 (2) 3.45 0 ( 2) 0.9 s t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b (3) 300 ns t f(sda) t f(scl) sda and scl fall time 300 20 + 0.1c b ( 3) 300 t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production 2. a device must internally provide an hold time of at least 300ns for the sda signal (r eferred to vihmin of the scl signal) to bridge the undefined region of the falling edge of scl 3. cb = total capacitance of one bus line, in pf sda scl t f(sda) t su(sp) t w(scll) t su(sda) t r(sda) t su(sr) t h(st) t w(sclh) t h(sda) t r(scl) t f(scl) t w(sp:sr) start repeated start stop start
LIS3LV02DL mechanical and electrical specifications 17/48 2.4 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 6.0 v. table 8. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 6 v vdd_io i/o pins supply voltage -0.3 to vdd +0.1 v vin input voltage on any control pin (cs, scl/spc, sda/sdi/sdo, ck) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd=3.3 v) 3000g for 0.5 ms 10000g for 0.1 ms a unp acceleration (any axis, unpowered) 3000g for 0.5 ms 10000g for 0.1 ms t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c esd electrostatic discharge protection 4.0 (hbm) kv 200 (mm) v 1.5 (cdm) kv this is a mechanical shock sensitiv e device, improper handling can cause permanent damages to the part this is an esd sensitive device, improp er handling can cause permanent damages to the part
mechanical and electrical specifications LIS3LV02DL 18/48 2.5 terminology 2.5.1 sensitivity sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. as the sensor can measur e dc accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (point to the sky) and noting the output value again. by doing so, 1g acceleration is applied to the sensor. subtracting the larger output value from the smaller one and dividing the result by 2 leads to the actual sensitivity of the sensor. this value changes very little over temperature and also very little over time. the sensitivity tolerance describes the range of sensitivities of a large population of sensors. 2.5.2 zero-g level zero-g level offset (off) describes the deviation of an actual output signal from the ideal output signal if there is no acceleration present. a sensor in a steady state on a horizontal surface will measure 0g in x axis and 0g in y axis whereas the z ax is will measure 1g. the output is ideally in the middle of the dynamic range of the sensor (content of out registers 00h, 00h with 16 bit representation, data expressed as 2?s complement number). a deviation from ideal value in this case is called zero-g offset. offset is to some extent a result of stress to a precise mems sensor and therefore the of fset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?zero-g level change vs. temperature?. the zero-g level of an individual sensor is stable over lifetime. the zero-g level tolerance describes the range of zero-g levels of a population of sensors. 2.5.3 self test self test allows to test the mechanical and electric part of the sensor, allowing the seismic mass to be moved by means of an electrostatic test-force. the self test function is off when the self-test bit of ctrl_reg1 (control register 1) is programmed to ?0?. when the self-test bit of ctrl_reg1 is programmed to ?1? an actuation force is applied to the sensor, simulating a definite input acceleration. in this case the sensor outputs will exhibit a change in their dc levels which is related to the selected full scale and depending on the supply voltage through the device sensitivity. when self test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. if the output signals change within the amplitude specified inside ta b l e 3 or 4 then the sensor is working properly and the parameters of the interface chip are within the defined specification.
LIS3LV02DL functionality 19/48 3 functionality the LIS3LV02DL is a high performance, low-power, digital output 3-axis linear accelerometer packaged in an lga package. the complete device includes a sensing element and an ic interface able to take the information from the sensing element and to provide a signal to the external world through an i 2 c/spi serial interface. 3.1 sensing element a proprietary process is used to create a surface micro-machined accelerometer. the technology allows to carry out suspended s ilicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. to be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. when an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacit ive half-bridge. this imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor. at steady state the nominal value of the capacitors are few pf and when an acceleration is applied the maximum variation of the capacitive load is up to 100ff. 3.2 ic interface the complete measurement chain is composed by a low-noise capacitive amplifier which converts into an analog voltage the capacitive unbalancing of the mems sensor and by three ? analog-to-digital converters, one for each axis, that translate the produced signal into a digital bitstream. the ? converters are coupled with dedicated reconstruction filters which remove the high frequency components of the quantization noise and provide low rate and high resolution digital words. the charge amplifier and the ? converters are operated respectively at 61.5 khz and 20.5 khz. the data rate at the output of the reconstruction depends on the user selected decimation factor (df) and spans from 40 hz to 2560 hz. the acceleration data may be accessed through an i 2 c/spi interface thus making the device particularly suitable for direct interfacing with a microcontroller. the LIS3LV02DL features a data-ready signal (rdy) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in digital system employing the device itself. the LIS3LV02DL may also be configured to generate an inertial wake-up, direction detection and free-fall interrupt signal accordingly to a programmed acceleration event along the enabled axes.
functionality LIS3LV02DL 20/48 3.3 factory calibration the ic interface is factory calibrated for sensitivity (so) and zero-g level (off). the trimming values are stored inside the device by a non volatile structure. any time the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation. this allows the user to employ the device without further calibration.
LIS3LV02DL application hints 21/48 4 application hints figure 5. LIS3LV02DL electrical connection the device core is supplied through vdd line while the i/o pads are supplied through vdd_io line. power supply decoupling capacitors (100 nf ceramic, 10 f al) should be placed as near as possible to the pin 13 of the device (common design practice). all the voltage and ground supplies must be present at the same time to have proper behavior of the ic (refer to figure 7 ). it is possible to re move vdd maintaining vdd_io without blocking the communication busses. in this condition the measurement chain is powered off. the functionality of the device and the measured acceleration data is selectable and accessible through the i 2 c/spi interface.when using the i 2 c, cs must be tied high while sdo must be left floating. refer to dedicated application note for further information on device usage. the functions, the trasholds and the timing of the interrupt pin (int) can be completely programmed by the user through the i 2 c/spi interface. 4.1 soldering information the lga-16 package is compliant with the ecopack ? , rohs and ?green? standard. it is qualified for soldering heat resist ance according to jedec j-std-020c. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www.st.com/mems . direction of the detectable accelerations vdd_io cs scl/spc sda/sdi/sdo sdo rdy/int 10uf vdd digital signal from/to signal controller.signal?s levels are defined by proper selection of vdd_io 100nf gnd LIS3LV02DL (top view) 1 6 7 8 9 14 15 16 y 1 x z
digital interfaces LIS3LV02DL 22/48 5 digital interfaces the registers embedded inside the LIS3LV02DL may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pads. to select/exploit the i 2 c interface, cs line must be tied high (i.e connected to vdd_io). 5.1 i 2 c serial interface the LIS3LV02DL i 2 c is a bus slave. the i 2 c is employed to write the data into the registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. both the lines are connected to vdd_io through a pull-up resistor embedded inside the LIS3LV02DL. when the bus is free both the lines are high. the i 2 c interface is compliant wit h fast mode (400 khz) i 2 c standards as well as the normal mode. table 9. serial interface pin description pin name pin description cs spi enable i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) scl/spc i 2 c serial clock (scl) spi serial port clock (spc) sda/sdi/sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sdo spi serial data output (sdo) table 10. serial interface pin description term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
LIS3LV02DL digital interfaces 23/48 5.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the LIS3LV02DL is 0011101b. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the LIS3LV02DL behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a salve address is sent, once a slave acknowledge (sak) has bee n returned, a 8-bit sub-addre ss will be transmitted: the 7 lsb represent the actual register address while the msb enables address auto increment. if the msb of the sub field is 1, the sub (regis ter address) will be auto matically incremented to allow multiple data read/write. the slave address is completed with a read/write bit. if the bit was ?1? (read), a repeated start (sr) condition will have to be issued after the two sub-addr ess bytes; if the bit is ?0? (write) the master will transmit to the slave with di rection unchanged. table 11. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak table 12. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 13. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 14. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data data data
digital interfaces LIS3LV02DL 24/48 data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other function, it can hold the clock line, scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to ?1? while sub(6-0) represents the address of first register to read. in the presented communication format mak is master acknowledge and nmak is no master acknowledge. 5.2 spi bus interface the LIS3LV02DL spi is a bus slave. the spi allows to write and read the registers of the device. the serial interface interacts with the outside world with 4 wires: cs , spc , sdi and sdo . figure 6. read and write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiple of 8 in case of mu ltiple byte read/write. bit durati on is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs . cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7di6di5di4di3di2di1di0 do7 do6 do5 do4 do3 do2 do1 do0 ms
LIS3LV02DL digital interfaces 25/48 bit 0 : rw bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in latter case, the chip will drive sdo at the start of bit 8. bit 1 : ms bit. when 0, the address will remain unch anged in multiple r ead/write commands. when 1, the address will be auto increment ed in multiple r ead/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (wri te mode). this is the data that will be written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the da ta that will be read from the device (msb first). in multiple read/write comman ds further blocks of 8 clock periods will be added. when ms bit is 0 the address used to read/write data remains the same for every block. when ms bit is ?1? the address used to read/write data is incremented at every block. the function and the behavior of sdi and sdo remain unchanged. 5.2.1 spi read figure 7. spi read protocol the spi read command is performed with 16 clock pulses. multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the da ta that will be read from the device (msb first). bit 16-... : data do(...-8). further da ta in multiple byte reading. cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms
digital interfaces LIS3LV02DL 26/48 figure 8. multiple bytes spi read protocol (2 bytes example) 5.2.2 spi write figure 9. spi write protocol the spi write command is performed with 16 cl ock pulses. multiple by te write command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : write bit. the value is 0. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (wri te mode). this is th e data that will be writ ten inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writing. figure 10. multiple bytes spi write protocol (2 bytes example) cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 do15 do14 do13 do12 do11 do10 do9 do8 ms cs spc sdi rw di7 di6 di5 di4 di3 di2 di1 di0 ad5 ad4 ad3 ad2 ad1 ad0 ms cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 di15 di14 di13 di12 di11 di10 di9 di8 ms
LIS3LV02DL digital interfaces 27/48 5.2.3 spi read in 3-wires mode 3-wires mode is entered by sett ing to ?1? bit sim (spi serial interface mode selection) in ctrl_reg2. figure 11. spi read protocol in 3-wires mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the da ta that will be read from the device (msb first). multiple read command is also available in 3-wires mode. cs spc sdi/o rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms
register mapping LIS3LV02DL 28/48 6 register mapping the table given below provides a listing of the 8 bit registers embedded in the device and the related addresses. table 15. registers address map register name type register address default comment binary hex rw 0000000 - 0001110 00 - 0e reserved who_am_i r 0001111 0f 00111010 dummy register rw 0010000 - 0010101 10-15 reserved offset_x rw 0010110 16 calibration loaded at boot offset_y rw 0010111 17 calibration loaded at boot offset_z rw 0011000 18 calibration loaded at boot gain_x rw 0011001 19 calibration loaded at boot gain_y rw 0011010 1a calibration loaded at boot gain_z rw 0011011 1b calibration loaded at boot 0011100 -0011111 1c-1f reserved ctrl_reg1 rw 0100000 20 00000111 ctrl_reg2 rw 0100001 21 00000000 ctrl_reg3 rw 0100010 22 00001000 hp_filter reset r 0100011 23 dummy dummy register 0100100-0100110 24-26 not used status_reg rw 0100111 27 00000000 outx_l r 0101000 28 output outx_h r 0101001 29 output outy_l r 0101010 2a output outy_h r 0101011 2b output outz_l r 0101100 2c output outz_h r 0101101 2d output r 0101110 2e reserved 0101111 2f not used ff_wu_cfg rw 0110000 30 00000000 ff_wu_src rw 0110001 31 00000000 ff_wu_ack r 0110010 32 dummy dummy register 0110011 33 not used ff_wu_ths_l rw 0110100 34 00000000
LIS3LV02DL register mapping 29/48 registers marked as reserved must not be changed. the writing to those registers may cause permanent damages to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered-up. ff_wu_ths_h rw 0110101 35 00000000 ff_wu_duration rw 0110110 36 00000000 0110111 37 not used dd_cfg rw 0111000 38 00000000 dd_src rw 0111001 39 00000000 dd_ack r 0111010 3a dummy dummy register 0111011 3b not used dd_thsi_l rw 0111100 3c 00000000 dd_thsi_h rw 0111101 3d 00000000 dd_thse_l rw 0111110 3e 00000000 dd_thse_h rw 0111111 3f 00000000 1000000-1111111 40-7f reserved table 15. registers address map (continued) register name type register address default comment binary hex
register description LIS3LV02DL 30/48 7 register description the device contains a set of registers which are used to control its behavior and to retrieve acceleration data. the registers 7.2 to 7.7 contain the factory calibration values, it is not necessary to change their value for normal device operation. 7.1 who_am_i (0fh) addressing this register the physical address of the device is returned. for LIS3LV02DL the physical address assigned in factory is 3ah. 7.2 offset_x (16h) 7.3 offset_y (17h) 7.4 offset_z (18h) table 16. register (0fh) w7 w6 w5 w4 w3 w2 w1 w0 table 17. register description (0fh) w7, w0 LIS3LV02DL physical address equal to 3ah table 18. register (16h) ox7ox6ox5ox4ox3ox2ox1ox0 table 19. register description (16h) ox7, ox0 digital offset trimming for x-axis table 20. register (17h) oy7 oy6 oy5 oy4 oy3 oy2 oy1 oy0 table 21. register description (17h) oy7, oy0 digital offset trimming for y-axis table 22. register (18h) oz7 oz6 oz5 oz4 oz3 oz2 oz1 oz0
LIS3LV02DL register description 31/48 7.5 gain_x (19h) 7.6 gain_y (1ah) 7.7 gain_z (1bh) 7.8 ctrl_reg1 (20h) table 23. register description (18h) oz7, oz0 digital offset trimming for z-axis table 24. register (19h) gx7gx6gx5gx4gx3gx2gx1gx0 table 25. register description (19h) gx7, gx0 digital gain trimming for x-axis table 26. register (1ah) gy7gy6gy5gy4gy3gy2gy1gy0 table 27. register description (1ah) gy7, gy0 digital gain trimming for y-axis table 28. register (1bh) gz7 gz6 gz5 gz4 gz3 gz2 gz1 gz0 table 29. register description (1bh) gz7, gz0 digital gain trimming for z-axis table 30. register (20h) pd1 pd0 df1 df0 st zen yen xen table 31. register description (20h) pd1, pd0 power down control (00: power-down mode; 01, 10, 11: device on) df1, df0 decimation factor control (00: decimate by 512; 01: decimate by 128; 10: decimate by 32; 11: decimate by 8)
register description LIS3LV02DL 32/48 pd1, pd0 bit allows to turn the device out of power-down mode. the device is in power- down mode when pd1, pd0= ?00? (default value after boot). the device is in normal mode when either pd1 or pd0 is set to 1. df1, df0 bit allows to select the data rate at which acceleration samples are produced. the default value is ?00? which corresponds to a data-rate of 40 hz. by changing the content of df1, df0 to ?01?, ?10? and ?11? the selected data-rate will be set respectively equal to 160 hz, 640 hz and to 2560 hz. st bit is used to activate the self test function. when the bit is set to one, an output change will occur to the device outputs (refer to tabl e 2 and 3 for specification) thus allowing to check the functionality of the whole measurement chain. zen bit enables the z-axis measurement channel when set to 1. the default value is 1. yen bit enables the y-axis measurement channel when set to 1. the default value is 1. xen bit enables the x-axis measurement channel when set to 1. the default value is 1. 7.9 ctrl_reg2 (21h) st self test enable (0: normal mode; 1: self-test active) zen z-axis enable (0: axis off; 1: axis on) ye n y-axis enable (0: axis off; 1: axis on) xen x-axis enable (0: axis off; 1: axis on) table 31. register description (continued) (20h) table 32. register (21h) fs bdu ble boot ien drdy sim das table 33. register description (21h) fs full scale selection (0: 2g; 1: 6g) bdu block data update (0: continuous update; 1: output regi sters not updated between msb and lsb reading) ble big/little endian selection (0: little endian; 1: big endian) boot reboot memory content ien interrupt enable (0: data ready on rdy pad; 1: interrupt events on rdy pad) drdy enable data-ready generation
LIS3LV02DL register description 33/48 fs bit is used to select full scale value. after the device power-up the default full scale value is +/-2g. in order to obtain a +/-6g full scale it is necessary to set fs bit to ?1?. bdu bit is used to inhibit output registers update between the reading of upper and lower register parts. in default mode (bdu = ?0?) the lower and upper register parts are updated continuously. if it is not sure to read faster than output data rate, it is recommended to set bdu bit to ?1?. in this way, after the reading of the lower (upper) register part, the content of that output registers is not updated until the upper (lower) part is read too. this feature avoids reading lsb and msb related to different samples. ble bit is used to select big endian or little endian representation for output registers. in big endian?s one msb acceleration value is located at addresses 28h (x-axis), 2ah (y-axis) and 2ch (z-axis) while lsb acceleration value is located at addresses 29h (x-axis), 2bh (y- axis) and 2dh (z-axis). in little endian repres entation (default, ble=?0?) the order is inverted (refer to data register description for more details). boot bit is used to refresh the content of internal registers stored in the flash memory block. at the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. if for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. when boot bit is set to ?1? the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. these values are factory trimmed and they are different for every accelerometer. they permit a good behavior of the device and normally they have not to be changed. at the end of the boot process the boot bit is set again to ?0?. ien bit is used to switch the value present on data-ready pad between data-ready signal and interrupt signal. at power up the data-ready signal is chosen. it is however necessary to modify drdy bit to enable data-ready signal generation. drdy bit is used to enable data-ready (rdy/int) pin activation. if drdy bit is ?0? (default value) on data-ready pad a ?0? value is present. if a data-ready signal is desired it is necessary to set to ?1? drdy bit. data-ready signal goes to ?1? whenever a new data is available for all the enabled axis. for example if z-axis is disabled, data-ready signal goes to ?1? when new values are available for both x and y axis. data-ready signal comes back to ?0? when all the registers containing values of the enabled axis are read. to be sure not to loose any data coming from the accelerometer data registers must be read before a new data-ready rising edge is gene rated. in this ca se data-ready signal will have the same frequency of the data rate chosen. sim bit selects the spi serial interface mode. when sim is ?0? (default value) the 4-wire interface mode is selected. the data coming from the device are sent to sdo pad. in 3-wire interface mode output data are sent to sda/sdi pad. das bit permits to decide between 12 bit right justified and 16 bit left justified representation of data coming from the device. the first case is the default case and the most significant bits are replaced by the bit representing the sign. sim spi serial interface mode selection (0: 4-wire interface; 1: 3-wire interface) das data alignment selection (0: 12 bit right justified; 1: 16 bit left justified) table 33. register description (continued) (21h)
register description LIS3LV02DL 34/48 7.10 ctrl_reg3 (22h) fds bit enables (fds=1) or bypass (fds=0) the high pass filter in the signal chain of the sensor. cfs1, cfs0 bits defines the coefficient hpc to be used to calculate the -3db cut-off frequency of the high pass filter: 7.11 hp_filter_reset (23h) dummy register. reading at this address zeroes instantaneously the content of the internal high pass-filter. read data is not significant. 7.12 status_reg (27h) table 34. register (22h) eck hpdd hpff fds res res cfs1 cfs0 table 35. register description (22h) eck external clock. default value: 0 (0: clock from internal oscillator; 1: clock from external pad) hpdd high pass filter enabled for direction detection. default value: 0 (0: filter bypassed; 1: filter enabled) hpff high pass filter enabled for free-fall and wake-up. default value: 0 (0: filter bypassed; 1: filter enabled) fds filtered data selection. default value: 0 (0: internal filter bypassed; 1: data from internal filter) cfs1, cfs0 high-pass filter cut-off frequency selection. default value: 00 (00: hpc=512 01: hpc=1024 10: hpc=2048 11: hpc=4096) f cutoff 0.318 hpc -------------- - odrx 2 ---------------- - ? = table 36. register (27h) zyxor zor yor xor zyxda zda yda xda table 37. register description (27h) zyxor x, y and z axis data overrun zor z axis data overrun yor y axis data overrun xor x axis data overrun
LIS3LV02DL register description 35/48 the content of this register is updated every odr cycle, regardless of bdu bit value in ctrl_reg2. 7.13 outx_l (28h) in big endian mode (bit ble in ctrl_reg2 set to ?1?) the content of this register is the msb acceleration data and depends on bit das in ctrl_reg2 register as described in the following section. 7.14 outx_h (29h) when reading the register in ?12 bit right justified? mode the most significant bits (15:12) are replaced with bit 11 (i.e. xd15-xd12=xd11, xd11, xd11, xd11). in big endian mode (bit ble in ctrl_reg2 set to ?1?) the content of this register is the lsb acceleration data. 7.15 outy_l (2ah) zyxda x, y and z axis new data available zda z axis new data available yda y axis new data available xda x axis new data available table 37. register description (continued) (27h) table 38. register (28h) xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 table 39. register description (28h) xd7, xd0 x axis acceleration data lsb table 40. register (29h) xd15 xd14 xd13 xd12 xd11 xd10 xd9 xd8 table 41. register description (29h) xd15, xd8 x axis acceleration data msb table 42. register (2ah) yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0
register description LIS3LV02DL 36/48 in big endian mode (bit ble in ctrl_reg2 set to ?1?) the content of this register is the msb acceleration data and depends on bit das in ctrl_reg2 register as described in the following section. 7.16 outy_h (2bh) when reading the register in ?12 bit right justified? mode the most significant bits (15:12) are replaced with bit 11 (i.e. yd15-yd12=yd11, yd11, yd11, yd11). in big endian mode (bit ble in ctrl_reg2 set to ?1?) the content of this register is the lsb acceleration data. 7.17 outz_l (2ch) in big endian mode (bit ble in ctrl_reg2 set to ?1?) the content of this register is the msb acceleration data and depends on bit das in ctrl_reg2 register as described in the following section. 7.18 outz_h (2dh) when reading the register in ?12 bit right justified? mode the most significant bits (15:12) are replaced with bit 11 (i.e. zd15 -zd12=zd11, zd11, zd11, zd11). table 43. register description (2ah) yd7, yd0 y axis acceleration data lsb table 44. register (2bh) yd15 yd14 yd13 yd12 yd11 yd10 yd9 yd8 table 45. register description (2bh) yd15, yd8 y axis acceleration data msb table 46. register (2ch) zd7 zd6 zd5 zd4 zd3 zd2 zd1 zd0 table 47. register description (2ch) zd7, zd0 z axis acceleration data lsb table 48. register (2dh) zd15 zd14 zd13 zd12 zd11 zd10 zd9 zd8 table 49. register description (2dh) zd15, zd8 z axis acceleration data msb
LIS3LV02DL register description 37/48 in big endian mode (bit ble in ctrl_reg2 set to ?1?) the content of this register is the lsb acceleration data. 7.19 ff_wu_cfg (30h) free-fall and inertial wake-up configuration register. 7.20 ff_wu_src (31h) table 50. register (30h) aoi lir zhie zlie yhie ylie xhie xlie table 51. register description (30h) aoi and/or combination of interrupt events. default value: 0. (0: or combination of interrupt events; 1: and combination of interrupt events) lir latch interrupt request. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) zhie enable interrupt request on z high event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt request on z low event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt request on y high event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt request on y low event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt request on x high event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt request on x low event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) table 52. register (31h) x ia zhzlyhylxhxl
register description LIS3LV02DL 38/48 7.21 ff_wu_ack (32h) dummy register. if lir bit in ff_wu_cfg register is set to ?1?, a reading at this address allows the ff_wu_src register refres h. read data is not significant. 7.22 ff_wu_ths_l (34h) 7.23 ff_wu_ths_h (35h) table 53. register description (31h) ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) zh z high. default value: 0 (0: no interrupt; 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt; 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt; 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt; 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt; 1: x low event has occurred) table 54. register (34h) ths7 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 55. register description (34h) ths7, ths0 free-fall / inertial wake up acceleration threshold lsb table 56. register (35h) ths15 ths14 ths13 ths12 ths11 ths10 ths9 ths8 table 57. register description (35h) ths15, ths8 free-fall / inertial wake up acceleration threshold msb
LIS3LV02DL register description 39/48 7.24 ff_wu_duration (36h) this register sets the minimum duration of the free-fall/wake-up event to be recognized. 7.25 dd_cfg (38h) table 58. register (36h) fwd7 fwd6 fwd5 fwd4 fwd3 fwd2 fwd1 fwd0 table 59. register description (36h) fwd7, fwd0 minimum duration of the free-fall/wake-up event duration s () ff_wu_duration (dec) odr ----------------------------------------------------------------------- - = table 60. register (38h) iend lir zhie zlie yhie ylie xhie xlie table 61. register description (38h) iend interrupt enable on direction change. default value: 0 (0: disabled; 1: interrupt signal enabled) lir latch interrupt request into dd_src reg with the dd_src reg cleared by reading dd_ack reg. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)
register description LIS3LV02DL 40/48 direction-detector configuration register. 7.26 dd_src (39h) direction detector source register. xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) table 61. register description (continued) (38h) table 62. register (39h) x ia zhzlyhylxhxl table 63. register description (39h) ia interrupt event from direction change. (0: no direction changes detected; 1: direction has changed from previous measurement) zh z high. default value: 0 (0: z below thsi threshold; 1: z accel. exceeding thse threshold along positive direction of acceleration axis) zl z low. default value: 0 (0: z below thsi threshold; 1: z accel. exceeding thse threshold along negative direction of acceleration axis) yh y high. default value: 0 (0: y below thsi threshold; 1: y accel. exceeding thse threshold along positive direction of acceleration axis) yl y low. default value: 0 (0: y below thsi threshold; 1: y accel. exceeding thse threshold along negative direction of acceleration axis) xh x high. default value: 0 (0: x below thsi threshold; 1: x accel. exceeding thse threshold along positive direction of acceleration axis) xl x low. default value: 0 (0: x below thsi threshold; 1: x accel. exceeding thse threshold along negative direction of acceleration axis)
LIS3LV02DL register description 41/48 7.27 dd_ack (3ah) dummy register. if lir bit in dd_cfg register is set to ?1?, a reading at this address allows the dd_src register refresh. read data is not significant. 7.28 dd_thsi_l (3ch) 7.29 dd_thsi_h (3dh) 7.30 dd_thse_l (3eh) 7.31 dd_thse_h (3fh) table 64. register (3ch) thsi7 thsi6 thsi5 thsi4 thsi3 thsi2 thsi1 thsi0 table 65. register description (3ch) thsi7, thsi0 direction detection internal threshold lsb table 66. register (3dh) thsi15 thsi14 thsi13 thsi12 thsi11 thsi10 thsi9 thsi8 table 67. register description (3dh) thsi15, thsi8 direction detection internal threshold msb table 68. register (3eh) thse7 thse6 thse5 thse4 thse3 thse2 thse1 thse0 table 69. register description (3eh) thse7, thse0 direction detection external threshold lsb table 70. register (3fh) thse15 thse14 thse13 thse12 thse11 thse10 thse9 thse8 table 71. register description (3fh) thse15, thse8 direction detection external threshold msb
typical performance characteristics LIS3LV02DL 42/48 8 typical performance characteristics 8.1 mechanical characteristics at 25c figure 12. x-axis zero-g level at 3.3 v figure 13. x-axis sensitivity at 3.3 v figure 14. y-axis zero-g level at 3.3 v figure 15. y-axis sensitivity at 3.3 v ?60 ?40 ?20 0 20 40 60 0 2 4 6 8 10 12 14 16 18 20 zero?g level offset [mg] percent of parts [%] 940 960 980 1000 1020 1040 1060 1080 1100 1120 0 5 10 15 20 25 sensitivity [lsb/g] percent of parts [%] ?60 ?40 ?20 0 20 40 60 0 5 10 15 20 25 zero?g level offset [mg] percent of parts [%] 940 960 980 1000 1020 1040 1060 1080 1100 1120 0 5 10 15 20 25 sensitivity [lsb/g] percent of parts [%]
LIS3LV02DL typical performance characteristics 43/48 8.2 mechanical characteristics de rived from measurement in the -40c to +85c temperature range figure 16. z-axis zero-g level at 3.3 v figure 17. z-axis sensitivity at 3.3 v ?60 ?40 ?20 0 20 40 60 0 5 10 15 20 25 zero?g level offset [mg] percent of parts [%] 940 960 980 1000 1020 1040 1060 1080 1100 1120 0 5 10 15 20 25 30 sensitivity [lsb/g] percent of parts [%] figure 18. x-axis zero-g level change vs. temperature at 3.3 v figure 19. x-axis sensitivity change vs. temperature at 3.3 v ?1.5 ?1 ?0.5 0 0.5 1 1.5 0 2 4 6 8 10 12 14 16 18 20 zero?g level drift [mg/ o c] percent of parts [%] ?0.05 ?0.045 ?0.04 ?0.035 ?0.03 ?0.025 ?0.02 ?0.015 ?0.01 ?0.005 0 0 5 10 15 20 25 sensitivity drift [%/ o c] percent of parts [%]
typical performance characteristics LIS3LV02DL 44/48 8.3 electro-mechanical characteristics at 25c figure 20. y-axis zero-g level change vs. temperature at 3.3 v figure 21. y-axis sensitivity change vs. temperature at 3.3 v figure 22. z-axis zero-g level change vs. temperature at 3.3 v figure 23. z-axis sensitivity change vs. temperature at 3.3 v ?1 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 25 30 35 40 zero?g level drift [mg/ o c] percent of parts [%] ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 0 5 10 15 20 25 sensitivity drift [%/ o c] percent of parts [%] ?2.5 ?2 ?1.5 ?1 ?0.5 0 0.5 1 1.5 2 2.5 0 5 10 15 20 25 zero?g level drift [mg/ o c] percent of parts [%] ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0 5 10 15 20 25 30 sensitivity drift [%/ o c] percent of parts [%] figure 24. x and y axis zero-g level as function of supply voltage figure 25. z axis zero-g level as function of supply voltage 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 ?60 ?40 ?20 0 20 40 60 supply voltage [v] zero?g level [mg] 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 ?40 ?20 0 20 40 60 80 100 supply voltage [v] zero?g level [mg]
LIS3LV02DL typical performance characteristics 45/48 figure 26. current consumption in power- down mode (vdd=3.3 v) figure 27. current consumption in operational mode (vdd=3.3 v) ?5 ?2.5 0 2.5 5 0 5 10 15 20 25 30 35 current consumption [ua] percent of parts [%] 550 600 650 700 750 0 2 4 6 8 10 12 14 16 current consumption [ua] percent of parts [%]
package information LIS3LV02DL 46/48 9 package information in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack ? is an st trademark. ecopack ? specifications are av ailable at: www.st.com. figure 28. lga-16 mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a1 0.92 1 0.0394 a2 0.7 0.0276 a3 0.180 0.220 0.260 0.0071 0.0087 0.0102 d1 4.250 4.400 4.550 0.1673 0.1732 0.1791 e1 7.350 7.500 7.650 0.2894 0.2953 0.3012 e 1.0 0.0394 d 0.3 0.0118 l1 5.000 0.1969 n 2.5 0.0984 n1 1.2 0.0472 p1 0.965 0.975 0.985 0.0380 0.0384 0.0388 p2 0.64 0.65 0.66 0.0252 0.0256 0.0260 t1 0.75 0.8 0.85 0.0295 0.0315 0.0335 t2 0.45 0.5 0.55 0.0177 0.0197 0.0217 r 1.200 1.600 0.0472 0.0630 h 0.150 0.0059 k 0.050 0.0020 i 0.100 0.0039 s 0.100 0.0039 lga16 (4.4x7.5x1mm) l and g rid a rray package 7863679 b e1 p2 l1 t2 d1 p1 b a c i a3 r a2 a1 12 4 5 6 7 8 16 15 9 10 11 12 13 14 3 n1 e t1 s e n d detail a detail a metal pad seating plane solder mask opening i e c d d a e b i b a c h d k b a c h b a c i e k k (4 x)
LIS3LV02DL revision history 47/48 10 revision history table 72. document revision history date revision changes 15-feb-2006 1 initial release. 15-jan-2008 2 added two new sections: section 2.3: communication interface characteristics and section 8: typical performance characteristics . content reworked to improve readability
LIS3LV02DL 48/48 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2008 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of LIS3LV02DL

	To Download LIS3LV02DL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .